The present invention relates to a data transfer controller in communication control device, and more particularly to a continuous data transfer control extending over a plurality of channels in a direct memory access controller which has a plurality of channels. By way of example, the present invention relates to techniques which are effective when applied to a communication control LSI that performs data transmission control in accordance with communication protocols.
As a data transfer controller for lightening the burden of a processor in a data transfer control, a direct memory access controller has heretofore been employed. This controller acquires the mastership of a bus from the processor, thereby to perform the control of data transfer with a memory and various input/output circuits in place of the processor.
In general, transfer methods based on the direct memory access controller are broadly classified into a cycle steal method wherein the controller requests the bus mastership every data transfer of one word and returns the mastership to the processor after the end of its operation; and a burst method wherein, once the controller has acquired the bus mastership, it transfers the data of a plurality of words continuously, and the processor is in a wait status or the like. In the burst method, when the period of time for which the direct memory access controller occupies the bus is prolonged limitlessly, a lowering in the operating efficiency of the processor might be incurred. It is therefore desirable to limit the number of the words which are to be continuously transferred.
In a conventional system, a plurality of peripheral devices are used, so that the direct memory access controller has a plurality of channels and can perform the data transfer control by setting the address of a transfer goal and the number of transfer words for each individual channel. Heretofore, however, any measure for correlating the data transfer controls in the individual channels has not been taken. For example, let's consider a case where, when the data transfer control is proceeding through a channel allotted to a specified peripheral device, a data transfer request is made for another channel. Even in this case, when the operation of the channel subjected to data transfer earlier is ended, the bus mastership is abandoned, and handshake interfacing for acquiring the bus mastership anew is executed.
Incidentally, an example of literature which explains a direct memory access controller having a plurality of channels is "Hitachi Microcomputer Data Book, Peripheral LSI of 8/16-Bit Microcomputer," pp. 389-442, published by Hitachi, Ltd. in September 1985.
When, in the direct memory access controller having the plurality of channels, any measure for correlating the data transfer controls in the individual channels is not taken and bus mastership aquisition controls for the respective channels are completely independent, operations for abandoning the bus mastership and for acquiring the bus mastership anew are necessitated each time the data transfer control is shifted to another channel. This has led to the problem of lowering the data transfer efficiency, and, lowering the throughput of the system.
In particular, the inventor's study has revealed the following: In a system which must transfer relevant data items over a plurality of channels, for example, a system which includes a controller for controlling communications, it is required to load from a main memory, control information necessary for the controls of the transmission and reception of data through a circuit control unit, address information necessary for the data transfer control by the direct memory access controller, etc. Further, it is required to perform a transmission process in accordance with a received content. Therefore, it is frequent cases that the operations of transferring the various control information items and the data to-be-transmitted from the main memory to the communication controller and transferring the received data to the main memory are relevant to one another. When, on such an occasion, the data transfer cannot be effected continuously over the plurality of channels, the throughput of the system lowers drastically.